Extraction of trap densities in poly-Si thin-film transistors fabricated by solid-phase crystallization and dependence on temperature and time of post annealing

Trap densities in poly-Si thin-film transistors fabricated by solid-phase crystallization have been extracted by measuring low-frequency capacitance–voltage characteristics and using a novel extraction algorithm. Moreover, the dependence of the trap densities on temperature and time of post annealing has been evaluated. It is found that the trap densities are flatly distributed and very roughly 1018 cm−3 eV−1 near the midgap and become tail states near the conduction band. Furthermore, the trap densities can be reduced by increasing the temperature and time of the post annealing. This is brought by the extinction of crystal defects generated during the solid-phase crystallization.