| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 748377 | Solid-State Electronics | 2013 | 7 Pages |
The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility (μ0) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage (Vfb), threshold voltage (Vth) and subthreshold swing (S) of JLT devices was also discussed.
► Junctionless transistors (JLTs) with planar structures were fabricated on SOI wafers. ► JLT μ0 is limited by phonon and neutral defect scattering for long lengths. ► JLT μ0 is limited by Coulomb and neutral defect scattering for short lengths. ► The temperature dependence of Vfb and Vth is similar in JLT devices. ► The less short channel effect in subthreshold swing is a strong advantage of JLT.
