(1 1 0) and (1 0 0) Sidewall-oriented FinFETs: A performance and reliability investigation

The performance and reliability of (1 0 0) and (1 1 0) sidewall, silicon-on-insulator (SOI) FinFETs with a Hf-based gate dielectric were evaluated. Unlike the typical planar MOSFET mobility orientation dependence, (1 1 0) FinFET sidewalls do not impair electron mobility and result in good short channel performance compared to (1 0 0) FinFET sidewall devices. Hot carrier injection (HCI) degradation was also investigated with nMOS and pMOS high-κ FinFETs on both sidewall surface orientations. Impact ionization at the source, as well as at the traditional drain side, was found to enhance HCI degradation when gate voltage (Vg) = drain voltage (Vd). The degradation becomes more pronounced as the gate length decreases, with a negligible dependence on substrate orientation. However, the orientation dependence of negative bias temperature instability (NBTI) on FinFETs demonstrates that the (1 1 0) orientation is slightly worse than (1 0 0). The kinetics of ΔNIT(t) under negative bias stress conditions suggests the interface trap density (NIT) is generated by a mechanism similar to that in planar devices.

► (1 1 0) FinFET electron mobility and short channel performance are similar to (1 0 0). ► Impact ionization at both drain and source was found to enhance HCI degradation. ► NBTI results demonstrate that the (1 1 0) orientation is slightly worse than (1 0 0). ► The NBTI kinetics for generated interface traps (ΔNIT) is similar to planar devices.