Study of symmetric microstructures for CMOS multilayer residual stress

This study presents a fabrication-based approach to improve the curl-up effect in complementary metal oxide semiconductor (CMOS) multilayer large-area planar structures. Control of the residual stress of CMOS multilayer microstructures is necessary for development of microelectromechanical systems (MEMS) sensors such as accelerometers and micromirrors. In this work, 3D symmetric geometry can be used to overcome effectively the residual stresses in CMOS multilayer microstructures. To demonstrate this concept, a symmetric multilayer flat-plane is fabricated and release-etched using an isotropic plasma etching process. The isotropic etch characteristics and lateral undercut can be controlled using a chamber pressure of 0.47 ± 0.2 Torr. A flat-plane structure with an area of 500 μm × 500 μm is fabricated using multilayer materials, including four metal and three silicon dioxide layers. Based on this approach, the measured results show the residual stress effect can be minimized in CMOS multilayer microstructures, and furthermore the curl-up effect of flat-plane is less than 2 μm across the 500 μm × 500 μm area.