A 72% error reduction scheme based on temperature acceleration for long-term data storage applications: Cold flash and millennium memories

•Flexible-nLC scheme is proposed for long-term storage applications.•This paper investigates the optimal coding scheme for different conditions.•The experiment results show that the temperature dependence exists in retention time.•The activation energy with different W/E cycles and ECC is also investigated.

A solid-state drive (SSD) with 1Xnm triple-level cell (TLC) NAND flash is proposed for low cost data storage applications with long-term data-retention requirements. Specifically, cold data storage requires 20 years data-retention with 100 write/erase (W/E) cycles, whereas digital archive storage requires 1000 years retention time with 1 W/E cycle. To achieve these requirements, a flexible-nLC scheme is proposed to improve the reliability of 1Xnm TLC NAND flash (Yamazaki et al., 2015). The proposed scheme combines two schemes, n-out-of-8 level cell (nLC) (Tanakamaru et al., 2014) and asymmetric coding (AC) (Tanakamaru et al., 2012) with the addition of a vertical flag. By measuring 1Xnm TLC NAND flash memory, the proposed scheme reduces errors by 72% and 69% for digital archive and cold flash respectively, compared to the conventional nLC scheme.