Improvement of metal gate/high-k dielectric CMOSFETs characteristics by neutral beam etching of metal gate

For the metal gate patterning of metal gate/high-k dielectric complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), plasma induced damage (PID) was identified during the etching by a conventional reactive ion etching (RIE) and, a neutral beam etching (NBE) technique. NBE uses reactive radical beam instead of reactive ions for RIE. Improved device characteristics such as the mobility, the transconductance, subthreshold slope, and drain current could be observed. Particularly, the application of the NBE to PMOSFET was more effective than that to NMOSFET. This improvement was related to the decreased interface trap density at the gate dielectric of CMOSFEETs.

► For the metal gate etching of CMOSFETs, plasma induced charging damage was identified. ► It was etched by a conventional reactive ion etching and a neutral beam etching technique. ► Improved device characteristics such as the mobility, the Gm, SS, and ID could be observed. ► The results are due to the decreased interface trap density.