Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
7939199 | Superlattices and Microstructures | 2018 | 25 Pages |
Abstract
We develop a 2D analytical subthreshold model for nanoscale double-gate junctionless transistors (DGJLTs) with gate-source/drain underlap. The model is validated using well-calibrated TCAD simulation deck obtained by comparing experimental data in the literature. To analyze and control short-channel effects, we calculate the threshold voltage, drain induced barrier lowering (DIBL) and subthreshold swing of DGJLTs using our model and compare them with corresponding simulation value at channel length of 20Â nm with channel thickness tSi ranging 5-10Â nm, gate-source/drain underlap (LSD) values 0-7Â nm and source/drain doping concentrations (NSD) ranging 5-12Â ÃÂ 1018Â cmâ3. As tSi reduces from 10 to 5Â nm DIBL drops down from 42.5 to 0.42Â mV/V at NSDÂ =Â 1019Â cmâ3 and LSDÂ =Â 5Â nm in contrast to decrement from 71 to 4.57Â mV/V without underlap. For a lower tSiDIBL increases marginally with increasing NSD. The subthreshold swing reduces more rapidly with thinning of channel thickness rather than increasing LSD or decreasing NSD.
Related Topics
Physical Sciences and Engineering
Materials Science
Electronic, Optical and Magnetic Materials
Authors
Debapriya Roy, Abhijit Biswas,