Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
8175310 | Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment | 2014 | 5 Pages |
Abstract
We have designed an ASIC for use in a parallel optical engine for a new layer of the ATLAS pixel detector in the initial phase of the LHC luminosity upgrade. The ASIC is a 12-channel VCSEL (Vertical Cavity Surface Emitting Laser) array driver capable of operating up to 5Â Gb/s per channel. The ASIC is designed using a 130Â nm CMOS process to enhance the radiation-hardness. A scheme for redundancy has also been implemented to allow bypassing of a broken VCSEL. The ASIC also contains a power-on reset circuit that sets the ASIC to a default configuration with no signal steering. In addition, the bias and modulation currents of the individual channels are programmable. The performance of the first prototype ASIC up to 5Â Gb/s is satisfactory. Furthermore, we are able to program the bias and modulation currents and to bypass a broken VCSEL channel. We are currently upgrading our design to allow operation at 10Â Gb/s per channel yielding an aggregated bandwidth of 120Â Gb/s. Some preliminary results of the design will be presented.
Keywords
Related Topics
Physical Sciences and Engineering
Physics and Astronomy
Instrumentation
Authors
K.K. Gan, P. Buchholz, H.P. Kagan, R.D. Kass, J. Moore, D.S. Smith, A. Wiese, M. Ziolkowski,