Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
8901580 | Applied Mathematics and Computation | 2018 | 12 Pages |
Abstract
We construct logical gates via topology optimisation (aimed to solve a station problem of heat conduction) of a conductive material layout. Values of logical variables are represented by high and low values of a temperature at given sites. Logical functions are implemented via the formation of an optimum layout of conductive material between the sites with loading conditions. We implement and and xor gates and a one-bit binary half-adder.
Related Topics
Physical Sciences and Engineering
Mathematics
Applied Mathematics
Authors
Alexander Safonov, Andrew Adamatzky,