Poly-Si gate engineering for advanced CMOS transistors by germanium implantation

Standard gate materials are compared to Ge implanted poly-Si and deposited poly-SiGe. It is demonstrated in this paper that the electrical resistance of the gate is significantly reduced via the use of poly-SiGe (from 30% to 40% decrease in resistance). Similarly, we show via specific optimization that localized Ge implantation is also suitable to reduce gate resistance. Physical characterizations are performed to determine the “root” causes at the origin of these improvements. In line with future publications showing strong benefits on CMOS device performance, grain size effects seem to be the main mechanisms explaining the measured improvement.