| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 10330388 | Future Generation Computer Systems | 2005 | 14 Pages |
Abstract
As current hardware performance counters do not give sufficient user relevant information, new hardware monitors are designed that provide more detailed information about the cache utilization related to the data structures and code blocks in the user program. The expense of the hardware and software realization will be assessed to minimize the risk of a real implementation of the investigated monitors. The usefulness of the hardware monitors is evaluated by a cache simulator.
Related Topics
Physical Sciences and Engineering
Computer Science
Computational Theory and Mathematics
Authors
Thomas Brandes, Helmut Schwamborn, Michael Gerndt, Jürgen Jeitner, Edmond Kereku, Martin Schulz, Holger Brunst, Wolfgang Nagel, Reinhard Neumann, Ralph Müller-Pfefferkorn, Bernd Trenkler, Wolfgang Karl, Jie Tao, Hans-Christian Hoppe,