Designing leakage tolerant, low power wide-OR dominos for sub-130Â nm CMOS technologies

In this paper, we discuss the design of leakage tolerant wide-OR domino gates for deep submicron (DSM), bulk CMOS technologies. Technology scaling is resulting in a 3×-5× increase in transistor IOFF/μm per generation causing 15-30% degradation in the noise margin of high performance domino gates. We investigate several techniques that can improve the noise margin of domino logic gates and thereby ensure their reliable operation for sub-130 nm technologies. Our results indicate that, selective usage of dual VTH transistors shows acceptable energy-delay tradeoffs for the 90 nm technology. However, techniques like supply voltage (Vcc) reduction or using non-minimum Le transistors are required in order to ensure robust and low power operation of wide-OR domino designs for the 70 nm generation.