Article ID Journal Published Year Pages File Type
545538 Microelectronics Journal 2016 7 Pages PDF
Abstract

This paper presents an optimized AC–DC converter designed in 65 nm low power process technology. Two topologies of the AC–DC converter are designed, namely, Bias-Flip rectifier and Voltage Doubler. The design is part of a piezo electric energy harvesting system targeting wearable electronics. Voltage doubler and full-bridge rectifier are fabricated to support a start-up mechanism while the bias-flip rectifier supports higher efficiency for the normal operation mode. Using a piezo electric energy harvester mounted on a shaker and operated at 4.5 Hz, the maximum extracted power from the voltage doubler is measured as 79.8 nW at 0.21 g. In addition, the maximum extracted power from the full-bridge rectifier is measured as 22.2 nW. As such, voltage doubler is more efficient than full-bridge rectifier by 71%. The experiment uses MIDE V22BL piezo electric harvester with 25 Hz resonance frequency. However, the harvester was used at 4.5 Hz (human frequency) which degrade the energy extracted from the harvester. If another harvester was designed to tune to lower frequency, higher energy level can be extracted. Another contribution in this paper is to compare the on-chip voltage doubler to board level with discrete components. Our experimental results show 11% improvement in efficiency for the on-chip design compared to off-chip for the same input power. The combined bias-flip rectifier and voltage doubler support energy autonomous systems where no start-up power is needed.

Related Topics
Physical Sciences and Engineering Computer Science Hardware and Architecture
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