Robustness enhancement through chip-package co-design for high-speed electronics

The low interaction between chip and package design has an increasingly limiting effect on the system performance. In this paper, the chip-package co-design flow is presented. We address robustness enhancement under the package and interconnection constraints as well as process, voltage, and temperature (PVT) variations by using impedance control, optimal pins assignment and transmitter equalization. From the simulation results we find that without on-chip digital compensation circuit, the variation of the driver's output impedance is 37% under different PVT conditions. However, it is only 5% when digital compensation circuit is used. Through optimal pins assignment the effective inductance of the pins is reduced. When power and ground pins are used as shielding pins, crosstalk is also decreased by 10 dB. Transmitter equalization effectively decreases inter-symbol interference caused by interconnection attenuation and dispersion. In our design example we find that without equalization the eye-diagram is almost closed at the receiver end. On the other hand with one-tap pre-emphasis equalization the eye-diagram is open and has a height of 90 mV and a width of 140 ps. It is also found that there is a clear optimal window for high data rate in this design. Without a chip-package co-design such an optimal window will not be found.