Influence of transient flow and solder bump resistance on underfill process

The underfill flow process is one of the important steps in Microsystems technology. One of the best known examples of such a process is with the flip-chip packaging technology which has great impact on the reliability of electronic devices. For optimization of the design and process parameters or real-time feedback control, it is necessary to have a dynamic model of the process that is computationally efficient yet reasonably accurate. The development of such a model involves identifying any factors that can be neglected with negligible loss of accuracy. In this paper, we present a study of flow transient behavior and flow resistance due to the presence of an array of solder bumps in the gap. We conclude (1) that the assumption of steady flow in the modeling of the flow behavior of fluids in the flip-chip packaging technology is reasonable, and (2) the solder bump resistance to the flow can not be neglected when the clearance between any two solder bumps is less than 60-70 μm. We subsequently present a new model, which extends the one proposed by Han and Wang in 1997 by considering the solder bump resistance to the flow.