Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
10364457 | Microelectronics Journal | 2011 | 10 Pages |
Abstract
The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Kaushik Bhattacharyya, Pradip Mandal,