Low power asynchronous circuit back-end design flow

This paper introduces a framework for the synthesis of low leakage power asynchronous circuits while maintaining performance requirements. In the proposed framework, a high-level description of the system is received and then the corresponding specification will be decomposed into smaller circuits which is possible to be directly mapped into predefined circuit templates. The proposed flow has the advantage of exploiting a new performance metric and presents an efficient methodology for static estimation of average performance of asynchronous circuits with choices at the template level. The leakage reduction is done via simultaneous supply voltage selection, multiple threshold voltage assignment and template sizing. The power reduction techniques are properly encoded in a quantum genetic algorithm and evaluated simultaneously. Experimental results are given for a number of 90 nm related benchmark circuits and show that this method reduces the total power by close to an order of magnitude, with no or negligible performance penalty.