Understanding and modeling of internal transient latch-up susceptibility in CMOS inverters due to microwave pulses

This paper analyzes the dependencies of the latch-up sensitivity of the CMOS inverter on the pulse width and the pulse repetition frequency (PRF) of the microwave pulse. Two physics-based models are presented to investigate the microwave pulse triggered latch-up effect and allow IC designers to identify the worst-case testing condition with the combination of the pulse width and the PRF. In model derivation, the continuity equation for electrons is solved with different boundary conditions for the excitation of a single shot microwave pulse and the repetitive microwave pulses, respectively. Device simulation and experimental data reported in literature have been used to verify the validity of these two analytical models. The theoretical model for the effects of pulse width shows that the latch-up sensitivity is an increasing function of the pulse width on a shorter time scale. If the pulse width increases steadily, the latch-up sensitivity becomes independent of the pulse width on a time scale of hundreds of nanoseconds. On the other hand, the theoretical model for the effects of PRF indicates that the latch-up sensitivity is also an increasing function of the PRF and the number of pulses, only if the PRF is far greater than the reciprocal of the minority carrier lifetime. Otherwise, the latch-up sensitivity is insensitive to the PRF or the number of pulses.