Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
10365220 | Microelectronics Journal | 2015 | 7 Pages |
Abstract
In the application for the space radiation environment, NML circuits face a reliability challenge mainly from their CMOS peripheral circuits, suffering from single event effects (SEE). An on-chip readout interface circuit (RIC) for NML circuit is designed based on dual-barrier magnetic tunnel junction (DB-MTJ). The sensitive nodes to SEE in RIC are analyzed. The SEU required critical charge in RIC is described. The impacts of energetic particle hitting time and technology node on the critical charge are studied. As the technology node scales down, the critical charge will significantly decrease. Two efficient hardening technologies for RIC are presented: local transistors׳ size and symmetrical load capacitances. By increasing local transistors׳ size or decreasing the load capacitance, the critical charge will be improved, which enhances the immunity to SEE.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Baojun Liu, Li Cai, Yan Li, Qiang Kang,