TLP analysis of 0.125 μm CMOS ESD input protection circuit

In this investigation, TLP ESD analysis shows that if a large input resistor is used in combination with a secondary ggNMOS clamp in the input protection circuitry, then the trigger voltage, Vt1, of the ggNMOS clamp is not a constant. The value is influenced by the size and properties of the input resistor, by current injection problems due to parallel resistive networks formed between the primary and secondary ESD circuits, by reverse bias diode leakage currents effects, and by source elevation effects due to voltage rises along the ESD ground bus.