| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 10365335 | Microelectronics Reliability | 2005 | 6 Pages |
Abstract
A highly scalable 2-bit nonvolatile memory (NVM) cell using two electrically isolated charge trapping sites is proposed and demonstrated by numerical device simulation. The operational mechanisms including read, program, erase and inhibit in an array structure are studied in detail. This double storage capability per single cell and highly scalable structure is very suitable for high density nanometric NVM applications.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Tsz Yin Man, Mansun Chan,