Simulation of flicker noise in gate-all-around Silicon Nanowire MOSFETs including interface traps

This paper presents a systematic investigation of flicker noise in Gate-all-around Silicon Nanowire MOSFET. The 1/f noise is simulated in the presence and absence of interface traps. Moreover the device is simulated under various distributions (Exponential, Gaussian, Uniform) of noise source. Nonuniformity in the interface of the oxide/semiconductor region as gave rise to increase the threshold voltage, there by increasing the leakage current. The effect of interface traps on different distribution has been explored in detail. The noise spectral density variations for various traps shows significant increase in flicker noise up to a magnitude of under 6 “dB” for weak signals. The simulated results matches with the calibrated experimental data.