Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
11023875 | Microelectronics Journal | 2018 | 21 Pages |
Abstract
The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100â¯V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p- SJ drift region pillar width of 0.3â¯Î¼m with a trench depth of 2.7â¯Î¼m achieves specific on-resistance (Ron,sp) of 0.21â¯mΩ.cm2 at a BV of 65â¯V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5â¯V and a gate voltage of 10â¯V.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Olujide Adenekan, Paul Holland, Karol Kalna,