Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects

This paper discusses the effect of jitter on the performance of clock retiming circuits for low-swing on-chip interconnects. For on-chip interconnects, the transmitter and receiver clocks are of the same frequency. Due to high latency of long interconnects, the phase synchronization is however lost, and clock retiming circuits are needed for sampling the data correctly. Correlated and uncorrelated jitter between the data and clock at the receiver affect the BER of such links. These effects are demonstrated with measurements on a coarse + fine correction type clock retiming circuit which was fabricated in 130 nm CMOS technology. These measurements, done at a clock frequency of 1.9 GHz, demonstrate the robustness of this circuit. Apart from BER, jitter also affects the settling time of these circuits, which is demonstrated. In the coarse + fine retiming circuit, the coarse tuning word can be pre-loaded to avoid this problem, and potentially reduce the settling time from more than 1 µs to under 200 ns.