Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
11023880 | Microelectronics Journal | 2018 | 7 Pages |
Abstract
This paper devises a novel Analog to Digital Converter (ADC) framework for energy-aware acquisition of analog signals with Logic-in-Memory capabilities. The beyond-CMOS hardware architecture has been designed to minimize the overall cost of signal acquisition. Spin-Hall Effect driven Domain Wall Motion (SHE-DWM) devices are utilized to realize the proposed framework called Spin-based Logic-In-Memory ADC (SLIM-ADC). Our simulation results indicate that the proposed SLIM-ADC offers â¼200â¯fJ energy consumption on average for each analog conversion or logic operation with up to 1â¯GHz speed. Furthermore, our results indicate that the proposed SLIM-ADC outperforms other state of the art spin-based ADC designs by offering â¼5.45â¯mW improved power dissipation on average. Additionally, a Majority Gate (MG)-based Full-Adder (MG-FA) is implemented using the proposed SLIM-ADC. Our results show that the proposed MG-FA offers â¼2.9-fold reduced power dissipation on average and â¼1.7-fold reduced delay on average compared to the state of the art Full-Adder designs reported herein.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Soheil Salehi, Ronald F. DeMara,