Area-efficient differential Gaussian circuit for dedicated hardware implementations of Gaussian function based machine learning algorithms

A simple and area-efficient differential Gaussian circuit is presented for machine learning dedicated hardware implementations, where Gaussian functions are needed, e.g. for artificial neural networks (as transfer function), support vector machines (as kernel function) and fuzzy logic (as membership function). The proposed Gaussian circuit consists of only 4 transistors. Simulations in the 0.18-μmμm CMOS UMC technology show that the proposed circuit is more accurate, less susceptible to the process variations and requires less on-chip area when compared to state-of-the-art.

► Gaussian circuit designed for hardware implementations of ML algorithms is proposed. ► The proposed circuit is more accurate than the state-of-the-art. ► The circuit requires smaller chip-area than the state-of-the-art. ► The proposed circuit is less susceptible to the process variations.