FPGA implementation of genetic vector quantizers

This paper presents a novel hardware architecture for genetic vector quantizer (VQ) design. It is based on steady-state genetic algorithm (GA) and adopts shift registers for accelerating mutation and crossover operations while reducing area cost. It also uses a pipeline for fitness evaluation. The proposed architecture has been embedded in a softcore CPU for physical performance measurement. Experimental results show that it is an effective alternative for VQ optimization attaining both high performance and low computational time.