Power-aware code scheduling assisted with power gating and DVS

•Our work applies power gating and dynamic voltage scaling together to save power.•We build a model to analyze a code and set parameters in code scheduling.•Our approach can outperform hardware power gating in terms of EDP and ED2P.•Our work can be applied to any compiler with architectural support.

Traditionally, code scheduling is used to optimize the performance of an application, because it can rearrange the code to allow the execution of independent instructions in parallel based on instruction level parallelism (ILP). According to our observations, it can also be applied to reduce power dissipation by taking advantage of the properties of existing low-power techniques. In this paper, we present a power-aware code scheduling (PACS), which is a code scheduling integrated with power gating (PG) and dynamic voltage scaling (DVS) to reduce power consumption while executing an application. In other words, from the viewpoint of compilation optimization, PG and DVS can be applied simultaneously to a code and their impact can be enhanced by code scheduling to further save power. The result shows that when compared with hardware power gating, the proposed PACS can outperform by more than 33% and 41% in terms of energy delay product and energy delay2 product for DSPStone and Mediabench.