| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 461459 | Microprocessors and Microsystems | 2014 | 15 Pages |
•Scalable architecture for manycore, tera-device computing.•Task-parallel programming models combining dataflow and stateful computations.•Parallel simulation of large-scale multi-node architectures.•Fault detection and recovery for task-level dataflow execution.
The improvements in semiconductor technologies are gradually enabling extreme-scale systems such as teradevices (i.e., chips composed by 1000 billion of transistors), most likely by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale project funded by the European Union, which addresses such challenges at once by leveraging the dataflow principles. This paper presents an overview of the research carried out by the TERAFLUX partners and some preliminary results. Our platform comprises 1000+ general purpose cores per chip in order to properly explore the above challenges. An architectural template has been proposed and applications have been ported to the platform. Programming models, compilation tools, and reliability techniques have been developed. The evaluation is carried out by leveraging on modifications of the HP-Labs COTSon simulator.
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