Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
462691 | Microprocessors and Microsystems | 2015 | 10 Pages |
This paper proposes and evaluates a de Bruijn inspired topology as an efficient alternative to the popular mesh topology for Network-on-Chips (NoCs). The proposed topology (1) provides logarithmic diameter for NoC, (2) offers better performance under uniform, hotspot, and matrix transpose traffic patterns and, (3) consumes lower energy for packet delivery, however, the proposed topology imposes the cost nearly equal to the mesh topology. In addition to the proposed topology, an analytical performance model is proposed in the paper to accelerate the evaluation process of the proposed topology. The model considers a network of M/G/1 queues and accurately estimates the average message latency as a widely used representative for the network performance. Results obtained from the analytical model are in good agreement with those of simulations for a wide range of working conditions such as various network sizes, different message lengths, and different traffic patterns.