Bandwidth and gain extension technique for CMOS distributed amplifiers using negative capacitance and resistance cell

This paper presents the design of a distributed amplifier simulated in a 0.13 µm CMOS model That use of a negative capacitance and resistance in order to increase gain and bandwidth. The proposed structure is used at the gate transmission line of the distributed amplifier. The negative capacitance at the gate transmission line decreases parasitic effects of gain cells and increases amplifier bandwidth and accordingly increases voltage gain. The generated negative resistance decreases transmission lines losses and increases bandwidth. The proposed 7-stage distributed amplifier consumes 97 mW from 1.8 V power supply while providing a voltage gain of 15 dB from 0.5-to-49 GHz with less than 0.3 dB in-band gain-variation. The circuit has a measured input and output return losses −7.9 dB and −9.4 dB, respectively, and an in-band noise-figure less than 4.7 dB, while circuit input and output are matched with 50 Ω resistance.