A power-optimized, area-efficient implementation of Connection-Then-Credit NoC physical layer

This paper discusses the implementation details of a complete NoC physical layer, basically, the Networks-on-Chip (NoC) routers, links and interfaces. A cycle-accurate RTL design details of complete NoC using a mesh-topology is presented with a special attention to the design of the NoC interface. The proposed implementation provides a complete end-to-end solution for an NoC system in a modular architecture, along with its advanced verification environment, to serve as a development and test platform for future NoC research. The paper also analyzes the performance of the Connection-Then-Credit (CTC) protocol and compares it to the conventional Credit-based (CB) protocol using standard traffic patterns, as well as its post-synthesis implementation results using TSMC 40 nm low-power CMOS technology. Through the addition of a low-power controller to the CTC-based NoC interfaces, our experimental results show a significant efficiency improvement in terms of power-savings, latency and area overhead. The CTC implementation achieved 21.46% saving in power consumption for the VOPD benchmark. In terms of gate-count, the CTC implementation of VOPD, MPEG, and MWD benchmarks achieved 14.40%, 34.05%, and 7.44% less gate counts, respectively.