Excess power elimination in high-resolution dynamic comparators

In this paper, a method is presented to reduce the power consumption of the two-stage dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier stage) amplifies the input differential voltage. Then the second stage (latch stage) is activated and finishes the comparison. When the comparison is about to finish, the balance of the positive feedback of the latch stage tends to tilt toward one of the outputs; after this, to the end of the comparison, there is no need for additional pre-amplification gain which causes excess power consumption. In this paper, a method is proposed to eliminate this part of power consumption. It is shown that while reducing the power consumption significantly, the method does not affect the dynamic behavior of the comparator such as speed or offset voltage. This method reduces the power consumption by 30% to 58%. Post Layout Simulations as well as analytical derivations and schematic simulations prove the beneficial performance of the proposed method.