A 5-bit 1-GS/s binary-search ADC in 90-nm CMOS

This study presented a 5-bit 1-GS/s binary-search analog-to-digital converter (ADC) that achieved low power and high-speed operation. A distributed track-and-hold circuit was applied to reduce the signal-to-noise-and-distortion ratio (SNDR) degradation caused by the comparator kickback noise and dynamic offset. A prototype 5-b 1-GS/s ADC was implemented in a 90-nm CMOS technology. It consumed 2.5 mW from a 1.2-V supply. The ADC core occupied an active area of 0.012 mm2. Operating at 800 MS/s, the measured peak SNDR and spurious-free dynamic range (SFDR) were 30.3 dB and 40 dB, respectively. At 1 GS/s, the measured peak SNDR and SFDR were 26 dB and 38 dB, respectively. The peak figure-of-merits are 98 fJ/conversion-step and 153 fJ/conversion-step at 800 MS/s and 1 GS/s, respectively.