4th order capacitively-coupled LC-based ΣΔ modulator

In this paper, we present the design and implementation of an RF bandpass ΣΔ modulator where the loop filter is a 4th order capacitively-coupled LC filter. A design methodology using coupling capacitor and the feedback Finite Impulse Response Digital-to-Analog Converter (FIRDAC) coefficients in order to obtain the desired Noise Transfer Function (NTF) is presented. The proposed capacitively-coupled bandpass LC ΣΔ is implemented in a 130 nm CMOS process. The fabricated chip, operating under a supply voltage of 1.2 V, has a varying center frequency range of 400-442 MHz with a corresponding sampling frequency range of 533-589 MHz. A maximum Signal-to-Noise Ratio (SNR) of 50 dB in a 4.5 MHz bandwidth for a power consumption of 20 mW was achieved. The effect of the clock jitter on the Analog-to-Digital Converter (ADC) performance is measured and presented.