MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells

This paper presents a modified low-voltage MOS current mode logic (MCML) exclusive-OR (XOR) gate. The proposed topology introduces multiple threshold voltage transistors in the triple-tail cell of a MCML XOR gate. This scheme allows reduction in the implementation area of a triple-tail cell and the logic gate employing it. The impact of employing multiple threshold voltage transistors on the operation of the XOR gate is investigated; and mathematical formulations for the static and delay parameters are derived. A design procedure based on the static model is put forward. The accuracy of the models is verified by designing and simulating the proposed XOR gate for wide operating conditions. The model parameters of TSMC 0.18 µm CMOS technology are used. An assessment in terms of implementation area and the process variations is conducted for the proposed and the available XOR gates. Finally, the performance of all the XOR topologies is compared for different design cases and the favorable cases are identified.