Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process

Large array devices (LAD) of MOSFETs are needed in most power ICs. NMOS transistors are used in current sinking while PMOS in current driving. Unlike the NMOS transistors, the high voltage PMOS transistors (HVPMOS) electrostatic discharge (ESD) self-protection of LAD for higher than 30 V applications are less extensively studied. In this paper, the device level improvements of the 60 V HVPMOS LAD of a 0.25 μm BCD process is studied to obtain good ESD protection margins. The effects of device and layout optimization guidelines are also examined. Furthermore, the developed approach is shown to be a low cost general solution for the HVPMOS LAD with poor ESD self-protection capability in a 0.25 μm BCD process.