Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
4971576 | Microelectronics Reliability | 2017 | 6 Pages |
Abstract
This paper presents a methodology for lifetime estimation of Front-End-of-Line (FEOL) and Middle-of-Line (MOL) time dependent dielectric breakdown (TDDB) in state-of-art logic circuits. The algorithm to extract vulnerable features of MOL-TDDB has been developed and implemented. A traditional 8-bit FFT circuit and a state-of-art Leon3 microprocessor are considered for lifetime calculation. The impact of different use scenarios on circuits is also investigated.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Kexin Yang, Taizhi Liu, Rui Zhang, Dae-Hyun Kim, Linda Milor,