Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
4971649 | Microelectronics Reliability | 2017 | 5 Pages |
Abstract
In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device.
Related Topics
Physical Sciences and Engineering
Computer Science
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Authors
A.N. Tallarico, S. Reggiani, P. Magnone, G. Croce, R. Depetro, P. Gattari, E. Sangiorgi, C. Fiegna,