| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 4971808 | Microelectronics Reliability | 2016 | 5 Pages |
Abstract
In nanotechnology domain, reliability is a fundamental concern in the design and manufacturing process of VLSI circuits. Thus, this paper presents a tool developed to evaluate the reliability of logic cells in order to provide a set of information to improve design robustness. The tool is able to evaluate logic cells under Single Event Transient (SET) faults and, also, permanent faults such as Stuck-On (SOnF) and Stuck-Open (SOF). The information produced by this tool help designers to choose the most reliable cells to be adopted in their designs.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Y.Q. de Aguiar, A.L. Zimpeck, C. Meinhardt, R. Reis,