NORA based TDC in 90 nm CMOS

•A time to digital converter with very high linearity.•Based on dynamic logic to improve resolution.•Ring oscillator based topology to increase dynamic range.•Test chip fabricated in 90 nm CMOS technology.•Experimental 25 ps resolution measured.

This paper investigates the idea to construct Time-to-Digital Converter (TDC) circuits based on dynamic precharged NORA delay elements. A self-charging technique is proposed in order to accommodate the dynamic delay elements in a ring-oscillator like structure. The employ of dynamic logic allows to reduce the TDC resolution with respect to previous TDCs based on standard CMOS logic. The ring-oscillator like topology imparts a very large dynamic range to the proposed circuit. In the paper a TDC, based on a Pseudo-differential topology, is presented, that is robust against PVT and mismatch variations. The TDC is fabricated in 90 nm CMOS technology, and presents a resolution of 25 ps. Experimental measurements confirm the effectiveness of the idea and show that the proposed TDCs exhibit low INL and a large dynamic-range when compared with state-of-the art circuits.