Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
541461 | Microelectronics Journal | 2013 | 19 Pages |
Abstract
This paper demonstrates the reversible fault tolerant logic synthesis for the Field Programmable Gate Array (FPGA) and its realization using MOS transistors. Algorithms to design a compact reversible fault tolerant n -to-2n2n decoder, 4n-to-n multiplexers, a random access memory and a Plessey logic block of the FPGA have been presented. In addition, several lower bounds on the numbers of garbage outputs, constant inputs and quantum cost of the FPGA have been proposed. The comparative results show that the proposed design is much better in terms of gate count, garbage outputs, quantum cost, delay, and hardware complexity than the existing approaches.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal,