Analysis and optimization of dynamically reconfigurable regenerative comparators for ultra-low power 6-bit TC-ADCs in 90 nm CMOS technologies

In this paper, the optimization and analysis of threshold configurable regenerative comparators (TC) for use in ultra-low power consumption ADCs is introduced (TC-ADC). Using a 90 nm CMOS technology, the obtained comparator achieves a 77% improvement in terms of power consumption (3μW) when compared with previously published TC comparators, while maintains the same full scale specification (±160 mv). The proposed design exhibits a delay time of 1.31 ns — a 20% of improvement — which allows achieving for a 6-bit TC-ADC up to 25 MS/s for a sampling period of 40 ns. Furthermore, offset, gain and non-linearity errors of a 6-bit TC-ADC is also analyzed for both perfectly matched devices and under the presence of manufacturing dependent device mismatch scenarios. The higher energy efficiency of the optimized comparator increases the linearity of the TC-ADC by a 50% in offset, gain, DNL and INL. Although, a mismatch analysis of 30 MonteCarlo simulations and 3σ device parameter variations exhibits a higher non-linearity for the threshold comparators, the gain, offset and DNL errors for the optimized one are diminished in a 37%, 12% and 17%, respectively.