Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
541734 | Microelectronics Journal | 2014 | 5 Pages |
Abstract
Real-time implementation of the transposition operation is particularly interesting in signal and image processing applications as they are dominated by matrix-based techniques. This paper presents a low-power transpose register array architecture that provides both row-wise and column-wise accesses. Reduction of power is achieved minimizing the switching activities of registers by means of a clock gating scheme without a significant extra logic overhead. Simulations demonstrate a power saving range of 40–70%, which is highly dependent on dimension and register size, all with a variable area cost from −2% up to 9%.
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Gustavo A. Ruiz, Mercedes Granda,