Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
541799 | Microelectronics Journal | 2013 | 8 Pages |
Abstract
This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process spreads and devices mismatches was designed in 0.35 μm CMOS technology to operate over dc to 20 MHz bandwidth and experimentally evaluated. The proposed limiting amplifier draws 280 μA from a 2-V supply and achieves a voltage gain of 72 dB.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
J. Ramos, J.L. Ausín, G. Torelli, J.F. Duque-Carrillo,