Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes

This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft errors. In this switch box architecture, the number of SRAM bits required for programming the switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated on several MCNC benchmarks using the VPR tool. Experimental results show that this architecture decreases the susceptibility of switch boxes to SEUs by about 20% on average compared to the traditional ones.