CMOS WTA maximum and minimum circuits with their applications to analog switch and rectifiers

This paper presents design of a voltage-mode multiple-inputs winner-take-all (WTA) maximum (max) and minimum (min) circuits. The proposed circuits are realized in a CMOS technology with low-component counts of transistors. They display usability of the proposed building block, where the maximum bandwidth of voltage follower is around 1 GHz and low-delay time is around 1.5 ns with high-input and low-output impedances. The THD obtained is around 0.8% within the 0.6Vp−p input range. The power dissipation of the proposed circuits is obtained to be around 0.62 mW with ±1.25 V power supplies. In applications, half-wave and full-wave rectifiers and analog switch are included. Computer simulation results by using SPICE program with TSMC 0.25 μm are carried out to show the performance of the proposed WTA max and min circuits, rectifiers and analog switch. In addition, the sample layout of the max circuit occupies an area of around 798 μm2 and post-layout simulation results are exhibited to concrete the pre-layout simulation results.