| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 541990 | Microelectronics Journal | 2010 | 7 Pages |
Abstract
The impact of operational amplifier (op-amp) phase margin on switched-capacitor (SC) sigma-delta modulator (ΣΔΜ) performance is investigated in this paper. An ad-hoc integrator settling model is developed and verified by circuit simulations performed in a commercial 0.35 μm CMOS technology. The model allows the effect of op-amp phase margin to be taken into account in ΣΔΜ behavioural analysis. Behavioural simulations of a typical single-bit second-order modulator are presented, as an example. As shown, the proposed analysis allows well-found specifications for the op-amp unity-gain frequency, slew rate and phase margin to be defined since the preliminary behavioural simulation phase.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo,