Designing robust threshold gates against soft errors

In applications where issues like power efficiency, high performance, and more noise tolerance are important, asynchronous design methodology can play a significant role. However, as a result of technology shrinkage, combinational asynchronous circuits have become vulnerable in presence of particle strikes. In this paper, we design robust quasi-delay insensitive (QDI) asynchronous circuits against soft errors. Null Convention Logic (NCL) gates used as one of the basic techniques in asynchronous circuits, are redesigned to increase their robustness against Single Event Upset (SEU). We analyze our design for various NCL structures and compare them with another design in Kuang et al. (2007) [4], and show that our proposed approach is more robust against SEU. The effect of some parameters such as power consumption, delay, and the influence of transistor sizing on soft error tolerance are discussed.