Design and performance evaluation of an adaptive FPGA for network applications

This paper presents the design, implementation and performance evaluation of a coarse-grain dynamically reconfigurable FPGA platform for multi-service edge and access network devices. The platform consists of two MicroBlaze RISC processors and a number of hardware co-processors used for the processing of packet payloads (Data Encryption Standard (DES) and Lempel–Ziv Compression). The co-processors can be connected either directly to the processors or using a shared bus. The functionality of the co-processors is dynamically reconfigured to meet the requirements of the network workload. The system has been implemented on the Xilinx Virtex II Pro platform and the network traces from real passive measurements have been used for performance evaluation. The use of dynamically reconfigurable co-processors for network applications shows that the performance speedup versus a static version varies from 12% to 35% in the best case and from 10% to 15% on average, depending on the network traffic fluctuation.